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The primary goals of this course are:
• Primary traits of MOS transistor and examines varied prospects for configuring inverter circuits
and facets of latch-up are thought of.
• Design processes are aided by easy ideas resembling stick and symbolic diagrams however the important thing factor is a
set of design guidelines, that are defined clearly.
• Primary circuit ideas are launched for MOS processes we are able to set out approximate circuit parameters
which drastically ease the design course of.
On the finish of this course the scholar can capable of:
• Perceive the properties of MOS energetic gadgets and easy circuits configured when utilizing them and the
cause for such encumbrances as ratio guidelines by which circuits will be interconnected in silicon.
• Know three units of design guidelines with which nMOS and CMOS designs could also be fabricated.
• Perceive the scaling components figuring out the traits and efficiency of MOS circuits in silicon.
Introduction and Primary Electrical Properties of MOS Circuits: Introduction to IC know-how, Fabrication
course of: nMOS, pMOS and CMOS. Ids versus Vds Relationships, Points of MOS transistor Threshold Voltage,
MOS transistor Trans, Output Conductance and Determine of Advantage. nMOS Inverter, Pull-up to Pull-down Ratio for
nMOS inverter pushed by one other nMOS inverter, and thru a number of cross transistors. Various types of
pull-up, The CMOS Inverter, Latch-up in CMOS circuits, Bi-CMOS Inverter, Comparability between CMOS and
BiCMOS know-how.
(Textual content Guide-1)
MOS and Bi-CMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Guidelines and Structure, Basic
observations on the Design guidelines, 2µm Double Steel, Double Poly, CMOS/BiCMOS guidelines, 1.2µm Double Steel,
Double Poly CMOS guidelines, Structure Diagrams of NAND and NOR gates and CMOS inverter, Symbolic DiagramsTranslation to Masks Type.
(Textual content Guide-1)

Primary Circuit Ideas: Sheet Resistance, Sheet Resistance idea utilized to MOS transistors and Inverters, Space
Capacitance of Layers, Customary unit of capacitance, Some space Capacitance Calculations, The Delay Unit, Inverter
Delays, Driving massive capacitive masses, Propagation Delays, Wiring Capacitances, Selection of layers.
Scaling of MOS Circuits: Scaling fashions and scaling components, Scaling components for gadget parameters, Limitations of
scaling, Limits on account of sub threshold currents, Limits on logic ranges and provide voltage on account of noise and present
density. Swap logic, Gate logic.
(Textual content Guide-1)

Chip Enter and Output circuits: ESD Safety, Enter Circuits, Output Circuits and L(di/dt) Noise, On-Chip
clock Technology and Distribution.
Design for Testability: Fault varieties and Fashions, Controllability and Observability, Advert Hoc Testable Design
Methods, Scan Primarily based Methods and Constructed-In Self Take a look at strategies.
(Textual content Guide-2)
FPGA Design: FPGA design movement, Primary FPGA structure, FPGA Applied sciences, FPGA families- Altera Flex
8000FPGA, Altera Flex 10FPGA, Xilinx XC4000 collection FPGA, Xilinx Spartan XL FPGA, Xilinx Spartan II
FPGAs, Xilinx Vertex FPGA. Case research: FPGA Implementation of Half adder and full adder.

Introduction to synthesis: Logic synthesis, RTL synthesis, Excessive stage Synthesis.
(Reference Textual content Guide-1)

Introduction to Low Energy VLSI Design: Introduction to Deep submicron digital IC design, Low Energy CMOS
Logic Circuits: Over view of energy consumption, Low –energy design by way of voltage scaling, Estimation and
optimisation of switching exercise, Discount of switching capacitance. Interconnect Design, Energy Grid and Clock
(Textual content Guide-2)
Textual content Books:
1. Necessities of VLSI Circuits and Programs – Kamran Eshraghian, Douglas and A. Pucknell and Sholeh
Eshraghian, Prentice-Corridor of India Non-public Restricted, 2005 Version.
2. CMOS Digital Built-in Circuits Evaluation and Design- Sung-Mo Kang, Yusuf Leblebici, Tata McGrawHill Schooling, 2003.
1. Superior Digital Design with the Verilog HDL, Michael D.Ciletti, Xilinx Design Collection, Pearson Schooling
2. Evaluation and Design of Digital Built-in Circuits in Deep submicron Expertise, 3’rd version, David